Particular embodiments generally relate to modeling for photolithographic processing and more particularly to contour generation for integrated circuit designs due to process variations.
In a conventional integrated circuit design process, a circuit designer begins with a conceptual idea of what functions an integrated circuit is to perform. The circuit designer then creates a circuit design on a computer and verifies it using one or more simulation tools to ensure that the circuit will operate as desired. The design at this stage may be represented by what is commonly viewed as a circuit schematic, but may also be represented by higher level abstractions within the computer.
These abstract designs are then converted to physical definitions of the circuit elements to be fabricated. These definitions, often called the drawn design of the circuit layout, represent the geometric boundaries for the physical devices to be fabricated—transistor gates, capacitors, resistive interconnecting wires, etc. A number of data formats have been created to represent these physical layouts, including Graphic Data System (GDS) II and OASIS™. Often, each physical layer of the circuit has a corresponding data layer to represent the polygonal boundaries of the elements in that layer.
Once the circuit layout has been defined, additional verification checks are performed. Some of these verification checks are to insure that the physical structures will correctly represent the desired electrical behavior. The devices in the layout may be extracted by a tool, such as an LVS, for Layout vs. Schematic or Layout vs. Source tool. Additional extraction of parasitic resistances and capacitances can be done, and the dynamic behavior of the circuit can be estimated for the layout as well. This step is traditionally called parasitic extraction. Then, the electrical behavior of the extracted device may be tested using a simulation tool, such as a Simulation Program with Integrated Circuit Emphasis (SPICE) tool. This is typically referred to as a parametric simulation.
In a parametric simulation, the width and length of a gate in a circuit layout may be used in a model to simulate the electrical behavior of the transistor. For example, the layout of a transistor may be back-annotated using the LVS. The SPICE simulator uses the width and length to simulate the electrical behavior of the transistor to verify its electrical behavior in silicon.
Due to process variations, the geometric shapes that are actually manufactured using a photolithographic process may vary from the circuit layout in the drawn design. Because of the process variations, the width and length from the drawn design may not provide an accurate simulation of the transistor. One solution for taking into account the process variations includes breaking up the area of the gate into an N number of segments. The width and length for each of these segments is then used in verifying the electrical behavior. This process, however, feeds N number of segments into the simulation. This is a computationally expensive and thus is undesirable.